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ltc4425 1 4425f typical application features description linear supercap charger with current-limited ideal diode and v/i monitor the ltc ? 4425 is a constant-current/constant-voltage linear charger designed to charge a 2-cell supercap stack from either a li-ion/polymer battery, a usb port, or a 2.7v to 5.5v current-limited supply. the part operates as an ideal diode with an extremely low 50m on-resistance making it suitable for high peak-power/low average power applications. the ltc4425 charges the output capacitors to an externally programmed output voltage in ldo mode at a constant charge current, or to v in in normal mode with a smart charge current pro? le to limit the inrush current until the v in to v out differential is less than 250mv. in addition the ltc4425 can be set to clamp the output voltage to 4.9v or 5.4v. charge current (v out current limit) is programmed by connecting a resistor between prog and gnd. the voltage on the prog pin represents the current ? owing from v in to v out for current monitoring. an internal active balancing circuit maintains equal voltages across each supercapacitor and clamps the peak voltage across each cell to a pin-selectable maximum value. the ltc4425 operates at a very low 20a quiescent current (shutdown current <3a) and is available in a low pro? le 12-pin 3mm 3mm dfn or a 12-lead msop package. charging 2-cell series supercapacitor from li-ion source applications n 50m ideal diode from v in to v out n smart charge current pro? le limits inrush current n internal cell balancer (no external resistors) n programmable output voltage (ldo mode) n programmable v in to v out current limit n continuous monitoring of v in to v out current via prog pin n low quiescent current: 20a n v in power fail, pgood indicator n 2.45v/2.7v cell protection shunts (4.9v/5.4v supercap max top-off voltage) n 3a peak current limit, thermal limiting n tiny application circuit, 3mm 3mm 0.75mm dfn and 12-lead msop packages n high peak power battery/usb powered equipment n industrial pdas n portable instruments/monitoring equipment n power meters, supercap backup circuits n pc card/usb modems l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ltc4425 gnd + C li-ion v in v out v in v in i monitor 1.5m 1.2m 2.2f pfi pfi_ret sel from c en 2.45v/2.7v 2k prog pfo 470k fb 1f 1f to high peak power load v mid 4425 ta01 + v in C v out (v) charge current (a) 0.6 0.5 4425 ta02 0 0.1 0.2 0.3 0.4 0 0.2 0.4 0.6 0.8 1 1/10 charge current current limited by pmos rdson ideal diode forward voltage = 15mv full charge current v fb = v in r prog = 2k charge current vs v in to v out differential
ltc4425 2 4425f pin configuration absolute maximum ratings v in , v out , v mid , fb, pfi_ret, pfo voltage .? 0.3v to 6v en, sel, pfi voltage ....?0.3v to max(v in , v out ) + 0.3v operating junction temperature ............? 40c to 125c (notes 1, 2) top view dd package 12-lead (3mm s 3mm) plastic dfn 12 11 8 9 10 4 5 3 2 1 v in v in v mid pfi pfo pfi_ret v out v out prog sel fb en 6 7 13 gnd t jmax = 125c, ja = 43c/w (note 3) exposed pad (pin 13) is gnd, must be soldered to pcb 1 2 3 4 5 6 v out v out prog sel fb en 12 11 10 9 8 7 v in v in v mid pfi pfo pfi_ret top view mse package 12-lead plastic msop 13 gnd t jmax = 125c, ja = 35c/w (note 3) exposed pad (pin 13) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc4425edd#pbf ltc4425edd#trpbf lfmq 12-lead (3mm 3mm) plastic dfn ?40c to 125c ltc4425idd#pbf ltc4425idd#trpbf lfmq 12-lead (3mm 3mm) plastic dfn ?40c to 125c ltc4425emse#pbf ltc4425emse#trpbf 4425 12-lead plastic msop ?40c to 125c ltc4425imse#pbf ltc4425imse#trpbf 4425 12-lead plastic msop ?40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ storage temperature range ..................? 65c to 150c lead temperature, msop only (soldering, 10 sec) ................................................ 300c
ltc4425 3 4425f electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c, v in = 3.8v. (note 4) symbol parameter conditions min typ max units v in operating supply range l 2.7 5.5 v i q(in) quiescent current from v in v in = v out 20 a i q(out) quiescent current from v out v in = v out 3a i sd quiescent current in shutdown en = 0 3 a ideal diode v fwd forward voltage 15 mv r fwd open loop forward on-resistance 50 m supercap charger v fb feedback voltage l 1.18 1.2 1.22 v i fb feedback pin input leakage 100 na i chg charge current in ldo mode (fb = 0v) r prog = 0.5k r prog = 5k 2 0.2 a a charge current in normal mode (fb = v in )r prog = 0.5k, v in C v out < 250mv r prog = 0.5k, v in C v out > 750mv 2 0.2 a a r prog = 5k, v in C v out < 250mv r prog = 5k, v in C v out > 750mv 200 20 ma ma v prog prog pin servo voltage in ldo mode fb < 1.2v 1.00 v h prog ratio of charge current to prog pin current 1000 ma/ma v prog prog pin servo voltage in normal mode (fb = v in )v in C v out < 250mv v in C v out > 750mv 1.00 0.1 v v i sc charger short-circuit current limit prog pin shorted to gnd, fb = 0 2 3 4 a t ss charger soft start time fb = 0 1.5 ms t lim junction temperature in constant temperature mode (note 5) v out = 0, fb = 0, r prog = 0.5k 105 c voltage clamps v clamp maximum voltage across the top capacitor v sel = lo v sel = hi l l 2.45 2.7 2.5 2.75 v v maximum voltage across the bottom capacitor v sel = lo v sel = hi l l 2.45 2.7 2.5 2.75 v v v rip v out clamp hysteresis if either capacitor reaches clamp voltage i.e. v out < v in 50 mv i sh(top) top shunt current r prog = 1k, (v out C v mid ) > v clamp 160 ma i sh(bot) bottom shunt current r prog = 1k, v mid > v clamp 140 ma
ltc4425 4 4425f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the current limit features of this part are intended to protect the ic from short term or intermittent fault conditions. continuous operation above the maximum speci? ed pin current rating may result in device degradation or failure. note 3: failure to solder the exposed backside of the package to the pc board ground plane will result in a thermal resistance much greater than 43c/w on the dd package and greater than 35c/w on mse package. note 4: the ltc4425e (e grade) is guaranteed to meet speci? cations from 0c to 85c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc4425i (i grade) is guaranteed over the full C40c to 125c operating junction temperature range. the junction temperature, t j , is calculated from the ambient temperature, t a , and power dissipation, p d , according to the formula: t j = t a + (p d ? ja c/w). note that the maximum ambient temperature is determined by speci? c operating conditions in conjunction with board layout, the rated thermal package thermal resistance and other environmental factors. note 5: v in to v out charge current is reduced by thermal foldback as junction temperature approaches 105c. electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c, v in = 3.8v. (note 4) symbol parameter conditions min typ max units leakage balancer v mid v mid output voltage v out = 3.6v 1.76 1.8 1.84 v v mid maximum current sourcing capability v mid < v out/2 , v mid < v clamp 0.7 ma v mid maximum current sinking capability v mid > v out/2 , v mid < v clamp 1.2 ma pfo , pfi_ret, pfi output low voltage ( pfo , pfi_ret) i pin = 5ma 65 mv pin leakage current ( pfo , pfi_ret) v pin = 5v, en = 0 1 a fb threshold voltage for power good (rising) ldo mode l 1.09 1.11 1.13 v input-to-output differential for power good (rising) normal mode 265 mv v pfi pfi threshold (falling) l 1.18 1.2 1.22 v pfi hysteresis 10 mv i pfi pfi pin input leakage 100 na power good timer delay 200 ms logic inputs (en, sel) v il logic low input voltage l 0.4 v v ih logic high input voltage l 1.2 v i ih input current high en, sel pins at 5.5v C1 1 a i il input current low en, sel pins at gnd C1 1 a
ltc4425 5 4425f typical performance characteristics charge current vs (v in Cv out ) differential prog pin voltage vs (v in C v out ) differential v in quiescent current vs temperature (v in v out ) charge current vs junction temperature charge current vs v out in thermal regulation v out quiescent current vs temperature (v in < v out ) ldo regulation voltage vs charge current ldo regulation voltage vs temperature charger fet on-resistance vs supply voltage i chg (ma) 0 3.255 voltage (v) 3.290 3.285 3.280 3.275 3.270 3.265 3.260 3.295 200 1000 1200 400 600 800 4425 g01 v in = 3.8v r prog = 1k v out set for 3.3v temperature (c) C45 3.277 v out (v) 3.285 3.284 3.283 3.282 3.281 3.280 3.278 3.279 3.286 C30 30 45 60 75 90 C15 0 15 4425 g02 v in = 3.8v v out set for 3.3v input voltage (v) 2.7 0 on-resistance (m) 70 60 50 40 30 10 20 80 3 4.2 4.5 4.8 3.3 3.6 3.9 4425 g03 25c 90c C45c v in to v out differential (v) 0 0 charge current (ma) 1000 800 600 200 400 1200 0.1 0.5 0.6 0.7 0.8 0.9 1 0.2 0.3 0.4 4425 g04 normal mode v in = 3.8v r prog = 1k ldo mode (fb grounded) v in to v out differential (v) 0 0 prog voltage (mv) 1000 800 400 200 600 1200 0.1 0.5 0.6 0.7 0.8 0.9 1 0.2 0.3 0.4 4425 g05 v in = 3.8v r prog = 1k normal mode ldo mode (fb grounded) temperature (c) C45 0 current (a) 20 15 5 10 25 C25 55 75 90 C5 15 35 4425 g06 v in = 3.8v v in = 2.7v temperature (c) C45 0 charge current (ma) 800 1000 600 200 400 1200 C30 30 45 60 75 90 105 120 C15 0 15 4425 g07 v in = 3.8v r prog = 1k, fb grounded output voltage (v) 0 0 charge current (ma) 2000 2500 1500 500 1000 3000 0.5 2.5 3 3.5 4 4.5 1 1.5 2 4425 g08 thermal regulation on-chip power dissipation ~4w case temp ~100c v in = 5v fb, prog pins shorted to gnd ambient temp 25c temperature (c) C45 0 current (a) 8 10 12 14 16 18 6 2 4 20 C25 55 75 90 C5 15 35 4425 g09 v out = 3.8v v out = 2.7v t a = 25c, unless otherwise noted.
ltc4425 6 4425f typical performance characteristics charge current vs voltage across top capacitor (v out C v mid ) charge current vs voltage across bottom capacitor (v mid ) output voltage transient step response waveform (ldo mode) output voltage waveform when v mid is shorted to gnd output voltage waveform when v mid is shorted to v out prog pin soft-start waveform (normal mode) logic inputs (en and sel) threshold voltage vs temperature open drain outputs (pfi_ret and pfo ) fet on-resistance vs temperature prog pin short circuit charge current vs temperature temperature (c) C45 0 voltage (v) 0.4 0.5 0.6 0.7 0.8 0.3 0.1 0.2 0.9 C25 55 75 90 C5 15 35 4425 g10 v in = 3.8v temperature (c) C45 0 resistance () 8 10 12 14 16 6 2 4 18 C25 55 75 C5 15 35 4425 g11 v in = 3.8v 90 v out to v mid differential (v) 1.6 0 charge current (ma) 2000 2500 3000 1500 500 1000 3500 1.7 2.1 2.2 2.3 2.4 2.5 1.8 1.9 2 4425 g12 prog pin grounded r prog = 1k sel = 0 v mid (v) 1.6 0 charge current (ma) 2000 2500 3000 1500 500 1000 3500 1.7 2.1 2.2 2.3 2.4 2.5 1.8 1.9 2 4425 g13 sel = 0 prog pin grounded r prog = 1k temperature (c) C45 C25 C5 15 35 55 75 2.70 charge current (a) 2.90 2.95 2.85 2.80 2.75 3.00 4425 g011a v in = 3.8v v out = 3.3v prog pin shorted to gnd 90 100ms/div supercap value = 0.55f v out (dc) = 2.45v 4425 g16 v in = 3.8v r prog = 1k sel = 0 v out 20mv/div ac-coupled 250ms/div supercap value = 0.55f v out (dc) = 2.45v 4425 g15 v in = 3.8v r prog = 1k v in = 3.8v r prog = 1k sel = 0 v out 20mv/div ac-coupled 500s/div 4425 g14 v out 20mv/div (ac-coupled) v in = 3.8v r prog = 500 supercap value = 0.55f v out (dc) = 3.3v i load 800ma 100ma 500s/div 4425 g18 v out (1v/div) v in = 5v r prog = 1k en t a = 25c, unless otherwise noted.
ltc4425 7 4425f pin functions v out (pin 1, 2): output pin of the charger. typically con- nects to the top of the 2-cell supercap stack. prog (pin 3): charge current program and charge current monitor pin. a resistor connected from prog to ground programs the charge current. in ldo mode, this pin always servos to 1v. however, if the charge current pro? le is turned on, this pin servos to a voltage between 1v and 0.1v depending on the input-to-output differential. in all cases, the voltage on this pin always represents the actual charge current. sel (pin 4): logic input to select one of the two possible clamp voltages (v clamp ). if the pin is a logic low, the maximum voltage across any supercap of the stack is 2.45v. if the pin is a logic high, it is 2.7v. do not ? oat this pin. fb (pin 5): in ldo mode, output voltage is programmed by a resistor divider from v out via the fb pin. in this mode, the voltage on this pin always servos to the internal reference voltage of 1.2v. if the fb pin is pulled up to v in , the ldo mode is disabled and the charge current pro? le mode is turned on. shorting the fb pin to gnd turns off charge current pro? le mode. do not ? oat this pin. en (pin 6): digital input to enable the charger. if this pin is a logic high, the part is enabled and it draws only 20a of quiescent current from the input or output when idle. if this pin is a logic low, the part is in shutdown mode and draws less than 3a. do not ? oat this pin. pfi_ret (pin 7): this pin connects to the bottom of the external resistor divider for the input power-fail compara- tor. in shutdown mode, an internal switch opens up this path to reduce the current drawn by the resistor divider. pfo (pin 8): open drain output of the power-fail com- parator. this pin is driven to logic low if at least one of the following conditions is true: (1) v in is less than a value programmed by an external divider via pfi, (2) v out has not reached within 7.5% of its ? nal programmed value in ldo mode, or (3) v out is not within 250mv of v in in charge current pro? le mode. when all these conditions are false for at least 200ms, this pin goes high impedance indicating that power is good. pfi (pin 9): input to the power-fail comparator. the input voltage below which pfo pin indicates a power-fail condi- tion can be programmed by connecting this pin to an external resistor divider between v in and pfi_ret pin. v mid (pin 10): connects to the midpoint of the 2-cell supercap stack. an internal leakage balancing ampli? er drives this pin to a voltage which is exactly half of v out . v in (pin 11, 12): input power pin. typically connected to a dc source like a li-ion/polymer battery or a usb port. this pin should be bypassed with a low-esr ceramic capacitor. gnd (exposed pad pin 13): gnd. the exposed pad should be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the part to achieve optimum thermal conduction.
ltc4425 8 4425f block diagram pshunt nshunt + C v out v in v out/2 v mid v sel prog r prog c big c big fb r lba r leakage balancer r fb2 r fb1 2.7v 2.45v 1.11v + C v out v in C 15mv ideal diode controller + C voltage clamp circuitry constant-voltage/ constant-current/ constant-temperature charger circuitry mpsw s 1000 mpsns s 1 bandgap reference charge current profile generator charge current 250mv 750mv v in C v out 1x 10x 1.2v 1.11v 0.1v oscillator 200ms timer pgood comparator pfi comparator charger enable + C v in v in v io v out + 250mv r pf1 r pf2 pfi en pfo pfi_ret + C pfc gnd v in C v out comparator 4425 bd 1.2v figure 1. ltc4425 block diagram
ltc4425 9 4425f operation the ltc4425 is a linear charger designed to charge a two-cell series supercap stack by employing a constant- current, constant-voltage, and constant-temperature architecture. it has two modes of operation: charge current pro? le mode (also referred to as normal mode) and ldo mode. in ldo mode, the ltc4425 charges the top of the stack to an externally programmed output voltage with a ? xed charge current that is also externally programmable. in charge current pro? le mode, the ltc4425 charges the top of the stack to the input voltage v in with a charge current that varies based on the input-to-output differential voltage. ldo mode in ldo mode, the output voltage v out is programmed by an external resistor divider network consisting of r fb1 and r fb2 via the fb pin and the charge current is programmed by an external resistor r prog via the prog pin. please refer to the block diagram shown in figure 1. the charger control circuitry consists of a constant- current ampli? er and a constant-voltage ampli? er. when the part is enabled to charge a discharged supercap stack, initially the constant-current ampli? er is in control and servos the prog pin voltage to 1v. the current through the prog resistor gets multiplied by approximately 1000, the ratio of the sense mosfet (mpsns) and the power mosfet (mpsw), to charge the supercap stack. as the output voltage v out gets close to the programmed value, the constant-voltage ampli? er takes over and backs off the charge current as necessary to maintain the fb pin voltage equal to an internal reference voltage of 1.2v. since the prog pin current is always about 1/1000 of the charge current, the prog pin voltage continues to give an indication of the actual charge current even when the constant-voltage ampli? er is in control. charge current pro? le or normal mode the ltc4425 is in charge current pro? le mode when the fb pin is shorted to the input voltage v in . in this mode of operation, the constant-voltage ampli? er is internally disabled but the charge current is still programmed by the external r prog resistor. the charger provides 1/10 of the programmed charge current if the input-to-output voltage differential (v in Cv out ) is more than 750mv to limit the power dissipation within the chip. as this differential voltage decreases from 750mv, the charge current increases linearly to its full programmed value when v out is within 250mv or closer to v in . as v out rises further, the voltage across the charger fet gets too small to support the full charge current. so the charge current gradually falls off and the charger fet enters into its triode (ohmic) region of operation (see figure 2). since the charger fet r ds(on) is approximately 50m, with a programmed charge current of 2a, the fet will enter the ohmic (triode) region and the charge current will start to fall off when v out is within about 100mv of v in . figure 2. different regions of charge current pro? le ideal diode control region ohmic region full charge current region linear charge current region 1/10 charge current region charge current (a) 0.3a 2a 0.2a 15 100 250 750 v in C v out (mv) 4425 f02 the ideal diode controller when the input-to-output differential approaches 15mv, the ideal diode controller takes over the control from the constant-current ampli? er and backs off the charge cur- rent by pulling up the gate of the charger fet as much as necessary to maintain a 15mv delta across the fet (see figure 2). as a result, v out can only be charged to 15mv below v in . in the event v in suddenly drops below v out , the controller will quickly turn the fet completely off to prevent any loss of charge due to the reverse ? ow of charge from the supercap back to the supply.
ltc4425 10 4425f operation thermal regulation in either mode, if the die temperature starts to approach 105c due to internal power dissipation, a thermal regula- tor limits the die temperature to approximately 105c by reducing the charge current. even in thermal regulation, the prog pin continues to give an indication of the charge current. the thermal regulation protects the ltc4425 from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without the risk of damaging the ltc4425 or the external components. another bene? t of this feature is that the charge current can be set according to typical, rather than worst-case, ambient temperatures for a given applica- tion with the assurance that the charger will automatically reduce the charge current in worst-case conditions. voltage clamp circuitry the ltc4425 is equipped with circuitry to limit the voltage across any supercap of the stack to a maximum allowable voltage v clamp . there are two preset voltages, 2.45v or 2.7v, for v clamp selectable by the sel pin. the sel pin should be set to logic low for lower v clamp voltage of 2.45v and to logic high for the higher v clamp voltage of 2.7v. if the voltage across the bottom capacitor, i.e., the v mid pin voltage reaches v clamp ? rst, an nmos shunt transistor turns on and starts to bleed charge off of the bottom capacitor to gnd. similarly, if the voltage across the top capacitor, v top , reaches the v clamp voltage ? rst, a pmos shunt transistor turns on and starts to bleed charge off of the top capacitor to the bottom one. when the voltage across any of the supercaps reaches within 50mv of v clamp , a transconductance ampli? er starts to cut back the charge current linearly. by the time any of the shunt devices are on, the charge current gets reduced to 1/10 of the programmed value and stays at this reduced level as long as the shunt device is on. this is to prevent the shunt devices from getting damaged by excessive heat. the comparators that control the shunt devices have a 50mv hysteresis meaning that when the voltage across either capacitor is reduced by 50mv, the shunt devices turn off and normal charging resumes with full charge current unless limited by any of the other am- pli? ers controlling the gate of the charger fet. in the event both capacitors exceed their maximum allowable voltage, v clamp , the main charger fet completely shuts off and both shunt devices turn on. both shunt devices are actually current mirrors guaranteed to shunt more current away than that coming through the charger fet. leakage balancing circuitry the ltc4425 is equipped with an internal leakage balancing ampli? er, lba, which servos the midpoint, i.e., v mid pin voltage, to exactly half of the output voltage, v out . however it has a very limited source and sink capability of approxi- mately 1ma. it is designed to handle slight mismatch of the supercaps due to leakage currents; not to correct any gross mismatch due to defects. the balancer is only active as long as there is an input present. the internal balancer eliminates the need for external balancing resistors. short-circuit current limit in the event the prog pin gets shorted to gnd, the ltc4425 limits the prog pin current to approximately 3ma which, in turn, limits the maximum charge current to about 3a. while in short-circuit, if one of the supercaps approaches within 50mv of its maximum allowable voltage, v clamp, a current-limit foldback circuit cuts back the short-circuit current limit to approximately 1/10 of its full value or to about 300ma. supply status monitor the ltc4425 includes an input power-fail comparator, pfc, which monitors the input voltage v in via the pfi pin. at any- time, if v in falls below a certain externally program-mable threshold, it reports the undervoltage situation by pulling down the open-drain output pfo low. this under-voltage threshold is programmed by connecting an external resis- tor divider network (consisting of r pf1 andr pf2 ) between v in and the pfi_ret pins. when the part is enabled, a low r ds(on) (approx. 13) internal pull-down transistor pulls the bottom end of r pf2 , i.e., the pfi_ret pin to gnd to complete the divider network. when the part is disabled, this transistor opens r pf2 from gnd, thereby saving the current drawn by the divider network. the power-fail com- parator has a built-in ? lter to reject any transient supply glitch that is less than 10s long.
ltc4425 11 4425f operation output status monitor the ltc4425 has an internal comparator to always monitor the output voltage v out . at any time, if v out falls below 7.5% of its ? nal programmed value in ldo mode or more than 250mv below the input voltage v in in charge current pro? le mode, the comparator reports the power- fail condition by pulling the same open-drain output pfo low. when both input and output voltages are good for at least 200ms, the pfo pin goes high impedance and can be pulled up to any external supply by a resistor to indicate a power good situation. in normal mode, the load should not exceed 1/10th of the programmed charge current until pfo is high. v out > v in operation if the en pin is pulled high and v in is below v out or ? oating, most of the circuitry including the voltage clamp circuitry is kept alive and the part draws about 20a from the output capacitors. however, the internal leakage balancer is turned off under this condition. shutdown mode the ltc4425 can be shut down by pulling the en pin low. in shutdown mode, very minimal circuitry is alive and the part draws less than 3a from the supply or from the output capacitors if the supply is not present. charge current soft-start the ltc4425 includes a soft-start circuit to minimize the inrush current at the start of a charge cycle. when a charge cycle is initiated, the charge current ramps from zero to full-scale over a period of approximately 1ms and this soft-start can be monitored by observing the prog pin voltage. this has the effect of minimizing the transient current load on the power supply during start-up. thermal shutdown the ltc4425 includes a thermal shutdown circuit in ad- dition to the thermal regulator. if for any reason, the die temperature exceeds 160c, the entire part shuts down. it resumes normal operation once the temperature drops by about 14c, to approximately 146c.
ltc4425 12 4425f programming the output voltage in ldo mode, the ltc4425 output voltage can be pro- grammed for any voltage between 2.7v and v in by using a resistor divider from v out pin to gnd via the fb pin such that: v out = v fb ? (1 + r fb1 /r fb2 ) where v fb is 1.2v. see figure 3. typical values for r fb are in the range of 40k to 1m. too small a resistor will result in a large quiescent current whereas too large a resistor coupled with fb pin capaci- tance will create an additional pole and may cause loop instability. applications information prog pin. the program resistor and the charge current are calculated using the following equations: r prog = 1000 ? (1v/i chrg ), i chrg = 1000 ? (1v/r prog ) where i chrg is the charge current out of the v out pin. the charge current out of the v out pin can be determined at any time by monitoring the prog pin voltage and using the following equation: i chrg = 1000 ? (v prog /r prog ) stability considerations in ldo mode, the ltc4425 supercapacitor charger has two principal control loops: constant-voltage and constant-current. the constant-voltage loop is stable when connected to a supercap of at least 0.2f. however, when disconnected from the supercap, the voltage loop requires at least 10f capacitance in series with 500 resistance for stability. in constant-current mode, the prog pin voltage is in the feedback loop, not the v out pin voltage. because of the additional pole created by the prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the charger is stable with a program resistor as high as 100k. however, any additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin is loaded with a capacitance, c prog , the following equation should be used to calculate the maximum resistance value for r prog : r prog 1/(2 ? 100khz ? c prog ) board layout considerations to be able to deliver maximum charge current under all conditions, it is critical that the exposed metal pad on the backside of the ltc4425s two packages have a good thermal contact to the pc board ground. correctly soldered to a 2500mm 2 double-sided 1 oz. copper board, the dfn package has a thermal resistance of approximately 43c/w. failure to make thermal contact between the exposed pad on the backside of the package and the copper board will result in a thermal resistance far greater than 43c/w. 4425 f03 ltc4425 pfi fb pfi_ret r pf1 r pf2 r fb1 r fb2 v in v in v out v out figure 3. programming output voltage and input threshold for power fail comparator. programming the input voltage threshold for power fail status indicator the input voltage below which the power fail status pin pfo indicates a power-fail condition is programmed by using a resistor divider from the v in pin to the pfi_ret pin via the pfi pin such that: v in , pfo = v pfi ? (1 + r pf1 /r pf2 ) where v pfi is 1.2v. see figure 3. typical values for r pf are in the range of 40k to 1m. in shutdown mode, this divider network is disconnected from ground via the pfi_ret pin to save the quiescent current drawn by the network. programming the charge current the ltc4425 charge current is programmed using a single resistor from the prog pin to ground. the charge current out of the v out pin is 1000 times the current out of the
ltc4425 13 4425f charge current reduction by the thermal regulator to protect the part against excessive heat generated by internal power dissipation, the ltc4425 is equipped with a thermal regulator which automatically reduces the charge current to maintain a maximum die temperature of 105c. ignoring the quiescent current, the power dissipation can be approximated by the following equation: p d = (v in C v out ) ? i chrg if ja is the thermal resistance and t a is the ambient temperature, then the die temperature can be calculated as: t die = t a + p d ? ja when the part is in thermal regulation, the die temperature is 105c and for a given v in and v out , the charge current can be determined by the following equation: i t vv chrg a in out ja = () ? 105 C C for example, if the ltc4425 in the dfn package is used in ldo mode to charge a completely discharged supercap stack (v out = 0v) at a room temperature of 25c from a 5v source, the charge current, at ? rst, will be limited to approximately: i cc vcw c ca ma chrg = () ? = = 105 25 50 43 80 215 372 C C/ / as the output voltage rises, the charge current will gradually rise to the full charge current programmed by the prog pin resistor as long as the constant-current loop is in control. if the ltc4425 is programmed for a charge current of 2a, the output voltage at which the part will deliver full charge current can be determined by the following equation: vv t i out in a chrg ja = ? C C 105 using the previous example, for full charge current, the output voltage has to rise to at least: vv c acw v c cv v out = () ? = = 5 105 25 243 5 80 86 407 C C / C / . applications information figure 4 shows the graph of charge current vs output voltage when the charge current pro? le is turned off by shorting the fb pin to gnd and the charge current is limited by thermal regulation. output voltage (v) 0 0 charge current(a) 2.0 1.5 1.0 0.5 2.5 156 234 4425 f04 v in = 5v r prog = 500 t a = 25c fb pin grounded thermal regulation 4.07v 105c 372ma figure 4. charge current vs output voltage under thermal regulation (ldo mode) c1 c sup v out c1 = c2 100f c2 4425 f05 ltc4425 v out v mid gnd figure 5. charging a single supercapacitor charging a single supercapacitor the ltc4425 can also be used to charge a single super- capacitor by connecting two series-connected matched ceramic capacitors with a minimum capacitance of 100f in parallel with the supercapacitor as shown in figure 5. refer to table 1 for supercapacitor manufacturers. table 1. supercapacitor manufacturers cap-xx www.cap-xx.com ness cap www.nesscap.com maxwell www.maxwell.com bussmann www.cooperbussmann.com avx www.avx.com illinois capacitor www.illcap.com tecate group www.tecategroup.com
ltc4425 14 4425f typical applications usb to high peak power 3.3v charging 3 aa alkaline to high peak power 3.3v charging v out v mid fb prog pfo 3.3v to load 2.1m 2.2f 1.2m 2k 470k 1f 1f v io ltc4425 en sel pfi_ret pfi v in 5v, 500ma usb 1.5m 1.2m 4425 ta03 c v out v mid fb prog pfo 3.3v, 2a to load current monitor 2.1m 1.2m 500 470k 1f 1f ltc4425 en sel pfi_ret pfi v in 4.5v to 3.6v 1.5m 1.2m 3 s aa 4425 ta04 c v io 2.2f li-ion high peak power battery buffer v out v mid prog pfo to load current monitor 0.6f 0.6f ltc4425 fb pfi pfi-ret en li-ion 1.5m 500 1.2m 470k sel v in 4425 ta04a + v io 2.2f
ltc4425 15 4425f typical applications usb c1 10f 0805 r1 100k c v bus d0 d1 d2 ntc chrg clprog prog gnd bat gate ldo3v3 v out c/x sw ltc4088 l1 3.3h m1 + li-ion r4 2k r3 2.94k c2 0.1f 0603 r5 8.2 r2 100k l1: coilcraft lps4018-332mlc m1: siliconix si2333 r2: vishay-dale nths0603n011-n1003f c1, c3: murata grm21br61a106ke19 c2: murata grm188r71c104ka01 csc: cap-xx hs203f instant-on c sc 0.55f hs203f v out v in pfi sel en pfo pfi_ret v mid v in fb prog gnd r6 2k c r8 1.2m r7 1.5m ltc4425 4425 ta05 c3 10f 0805 5 v v in load high current usb charging with power path control 3.3v peak-power/back-up supply c sc 0.55f hs203f v out v in pfi sel en pfo pfi_ret v mid v in fb prog gnd 2k c 1.2m 1.5m ltc4425 4425 ta05a sw1 pv in v in run/ss r t sw2 pv out v out fb ltc3533 10 f 5 v v in 5 v 340k 6.49k 100 f 47pf v out 3.3v 1.5a 200k 0.1 f 107k 330pf 4.7pf 2.2 h 33.2k 200k pgnd sgnd on off burst v c 2.2f
ltc4425 16 4425f ltc4425 v in fb pfi sel en pfo pfi_ret v out v mid prog gnd c sp1 1f c sp2 1f c r8 1.2m 1.5m 11k r6 2k v out sw i sense fb i lim v in 59k 28.7k gnd 2.2f lt3663 run boost off on 0.1f d1 22f 5v instant-on 6.8h d1: dfls240 csp1, csp2: 12v 4425 ta07 5v high-peak power, or backup supply 12v input to 5v outputs with input voltage monitoring typical applications c sp1 1f c sp2 1f 3.3v 5v v out v in v out (5v) v in shdn rt gnd v c fb sw boost pfi sel en pfo pfi_ret v mid fb prog gnd r6 2k 1.2m 2.1m c r8 1.2m r7 1.5m ltc4425 lt3505 4425 ta06 12v 10f 68pf 11.3k 61.1k 10h 0.1f d1 d2 69.8k 75k 70pf 1f d1: 1n4148 d2: mbrm140 csp1, csp2: cap-xx hs203f high peak- power load 12v to 5v/3.3v high peak power supply
ltc4425 17 4425f typical applications redundant high peak power battery supplies ltc4425 ltc4425 sel en pfo pfo fb pfi pfi_ret v in sel en fb pfi pfi_ret v in v out v mid v out v io v mid 1.2m 1.5m 2.2f prog prog 2k 500 470k 1.5m 3 s aa 1.2m 4425 ta08 usb to load bat power ok usb power ok 1f 1f c 2.2f
ltc4425 18 4425f package description 3.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad and tie bars shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.65 0.10 0.75 0.05 r = 0.115 typ 1 6 12 7 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd12) dfn 0106 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.23 0.05 0.25 0.05 2.25 ref 2.38 0.05 1.65 0.05 2.10 0.05 0.70 0.05 3.50 0.05 package outline pin 1 notch r = 0.20 or 0.25 s 45 chamfer 2.38 0.10 2.25 ref 0.45 bsc 0.45 bsc dd package 12-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1725 rev a)
ltc4425 19 4425f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. msop (mse12) 0608 rev b 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 C?0.38 (.009 C .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail b 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 123456 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev b) detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc package description
ltc4425 20 4425f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0510 ? printed in usa related parts part number description comments ltc3225-1 ltc3225 150ma supercapacitor charger programmable supercapacitor charger designed to charge two supercapacitors in series to a fixed output voltage (4.8v/5/3v selectable) lt3485-0/lt3485-1/ lt3485-2/lt3485-3 1.4a/0.7a/1a/2a photo? ash capacitor charger with output voltage monitor and igbt v in ; 1.8v to 10v, charge time = 3.7 seconds for the lt3485-0 (0v to 320v, 100f, v in = 3.6v), i sd < 1a, 3mm 3mm 10-lead dfn lt3750 capacitor charger controller charges any size capacitor, 10-lead ms package lt3751 capacitor controller with regulation charges any size capacitor, 4mm 5mm qfn-20 package typical application ltc4425 ltc3569 (ud package) v in fb pfi sel en pfo pfi_ret v out v out (5v) v mid prog gnd c sp1 1f c sp2 1f 8 4 6 c 11, 12 r7 1.5m r8 1.2m 9 5 7 3 13 10 1, 2 5v, 2a r6 500 sv in pv in , 1, 2, 3 sw1 pgnd, 1, 2, 3 sgnd sw2 sw3 pgood fb1 fb2 fb3 l2 2.2h 10f 20pf 750k 240k sw bias fb v c pg rt v in bd 10f 200k 28.7k l1 2.2h 22f 590k 20k gnd 2.2f lt3684 run boost 3.3v l3 2.5h 4.7f 20pf 300k 240k 1.8v l4 2.5h 4.7f 20pf 150k 240k 1.2v off on car battery d1 330pf 6v to 36v 0.1f en1 en2 en3 mode rt d1: diodes inc. dfls240 l1: sumida cdrh4d22/hp-2r2 l2: wurth 7440430022 l3, l4 wurth 744031002 csp1, csp2: cap-xx hs203f 4425 ta09 embedded automotive backup controller

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